1. Field of the Invention
The present invention relates to an integrated semiconductor memory device divided into a plurality of memory blocks, and more particularly, to a semiconductor device including memory blocks that have in a matrix array of plurality of memory cells and a decoding means suitable for the selection of memory cells.
2. Description of the Prior Art
Well known circuits for semiconductor memory devices are disclosed in pages 264-265 of the ISSCC Journal, published on 1987. This art of semiconductor technology forms the basis for the technological improvement represented by the present invention.
It is known in the art, as illustrated by a schematic block diagram of FIG. 1, to divide an integrated semiconductor memory device into a plurality of memory blocks to allow effective access to one memory cell in a high capacity memory. Such as arrangement reduces the delay required to access from main word line to block word line because memory cells are divided into a plurality of memory blocks. A certain memory cell is selected when a memory block selected among the divided plurality of memory blocks which ensures an improvement to the access time and power consumption by the memory device.
In the prior art form of a memory shown in FIG. 1, reference numerals 1, 2 . . . i each identify a memory block and each such block includes an array of memory cells arranged in the form of matrix. Each memory block is selected by a block selection signal BSWL.sub.1, BSWL.sub.2, . . . or BSWL.sub.i outputted from block selection decoder 10 in response to an input signal. A word line WL.sub.1, WL.sub.2 or WL.sub.n in memory blocks is selected by row selection signal MWL.sub.1, MWL.sub.2 . . . MWL.sub.n outputted from row decoder 11 in response to a row address input signal. In a high capacity memory circuit, when a memory cell array is divided into a plurality of memory blocks, word line selection logic circuits 12 are required and take the form of NOR logic or NAND logic circuits for decoding the divided blocks. NOR logic circuits 13 are illustrated in FIG. 1.
Such a logic circuit includes a plurality of transistors, and, more particularly, a NOR or NAND logic circuit requires four to six transistors to form the logic of the circuit. Therefore, when high capacity memory cells are fabricated, the chip area required to form the required logic circuits for selective access to the memory cells is increased and the speed at which the logic circuits operate is slower as compared with, for example, an inversion logic circuit. Moreover, the input gate capacitance of the logic circuits connected to each word line WL.sub.1, WL.sub.2 . . . WL.sub.n within the memory blocks cause the problem of deterioration to the high speed performance.